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74LV165 8-bit parallel-in/serial-out shift register
Product specification Supersedes data of 1997 May 15 IC24 Data Handbook 1998 May 07
Philips Semiconductors
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165
FEATURES
* Wide operating voltage: 1.0 to 5.5 V * Optimized for low voltage applications: 1.0 to 3.6 V * Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V * Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, * Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, * Asynchronous 8-bit parallel load * Synchronous serial input * Output capability: standard * ICC category: MSI
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr = tf 2.5 ns SYMBOL tPHL/tPLH fmax CI CPD PARAMETER Propagation delay CE, CP to Q7, Q7 PL to Q7, Q7 D7 to Q7, Q7 Maximum clock frequency Input capacitance Power dissipation capacitance per gate Tamb = 25C Tamb = 25C
DESCRIPTION
The 74LV165 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT165. The 74LV165 is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0Q1Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated.
CONDITIONS CL = 15 pF; VCC = 3.3 V
TYPICAL 18 18 14 78 3.5
UNIT ns MHz pF pF
VCC = 3.3 V VI = GND to VCC1
35
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi ) (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES 16-Pin Plastic DIL 16-Pin Plastic SO 16-Pin Plastic SSOP Type II 16-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C OUTSIDE NORTH AMERICA 74LV165 N 74LV165 D 74LV165 DB 74LV165 PW NORTH AMERICA 74LV165 N 74LV165 D 74LV165 DB 74LV165PW DH PKG. DWG. # SOT38-4 SOT109-1 SOT338-1 SOT403-1
PIN CONFIGURATION
PL CP D4 D5 D6 D7 Q7 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V CC
PIN DESCRIPTION
PIN NUMBER 1
CE D3 D2 D1 D0 DS Q7
SYMBOL PL CP Q7 GND Q7 DS D0 to D7 CE VCC
FUNCTION Asynchronous parallel load input (active LOW) Clock input (LOW to HIGH, edge-triggered) Complementary output from the last stage Ground (0 V) Serial output from last stage Serial data input Parallel data inputs Clock enable input (active LOW) Positive supply voltage
2 7 8 9 10 11, 12, 13, 14, 3, 4, 5, 6 15 16
SV00585
1998 May 07
2
853-1915 19349
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165
LOGIC SYMBOL
10 DS
FUNCTIONAL DIAGRAM
11 11 12 13 14 3 4 5 6 1 D0 D1 D2 D3 D4 D5 D6 D7 PL CP CE 15 2 15 CE Q7 Q7 9 7 2 CP 8-BIT SHIFT REGISTER PARALLEL- IN / SERIAL - OUT 10 DS Q7 Q7 9 7 1 PL D0 12 D1 13 D2 14 D3 3 D4 4 D5 5 D6 6 D7
SV00586 SV00588
LOGIC SYMBOL (IEEE/IEC)
1 SRG8 C2 [LOAD] G1 [SHIFT] >1 1 C3/ 3D 2D 2D
15 2 10 11 12 13 14 3 4 5 6
9 7
SV00587
LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
DS CP
D SD Q D SD Q D SD Q D SD Q D SD Q D SD Q D SD Q D SD Q
Q7 Q7
CE PL
CP FF0 RD
CP FF1 RD
CP FF2 RD
CP FF3 RD
CP FF4 RD
CP FF5 RD
CP FF6 RD
CP FF7 RD Q
SV00589
1998 May 07
3
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165
FUNCTION TABLE
INPUTS OPERATING MODES PL L Parallel load L H Serial Shift Hold "do nothing" H H CE X X L L H CP X X X DS X X l h X D0-D7 L H X X X Qn REGISTERS Q0 L H L H q0 Q1-Q6 L-L H-H q0-q5 q0-q5 q1-q6 OUTPUTS Q7 L H q6 q6 q7 Q7 H L q6 q6 q7
NOTES: H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level I = LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition X = don't care = LOW-to-HIGH clock transition
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb PARAMETER DC supply voltage Input voltage Output voltage Operating ambient temperature range in free air See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V CONDITIONS See Note 1 MIN 1.0 0 0 -40 -40 - - - - - - - - TYP 3.3 - - MAX 5.5 VCC VCC +85 +125 500 200 100 50 UNIT V V V C
tr, tf
Input rise and fall times
ns/V
NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL VCC "IIK "IOK "IO "IGND, "ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current - standard outputs DC VCC or GND current for types with - standard outputs Storage temperature range Power dissipation per package - plastic DIL - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) for temperature range: -40 to +125C above +70C derate linearly with 12 mW/K above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI < -0.5 or VI > VCC + 0.5V VO < -0.5 or VO > VCC + 0.5V -0.5V < VO < VCC + 0.5V CONDITIONS RATING -0.5 to +7.0 20 50 25 UNIT V mA mA mA
50 -65 to +150 750 500 400
mA C mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 May 07
4
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2 V VIH HIGH level Input voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 4.5 to 5.5 V VCC = 1.2 V VIL LOW level Input voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 4.5 to 5.5 VCC = 1.2 V; VI = VIH or VIL; -IO = 100A VCC = 2.0 V; VI = VIH or VIL; -IO = 100A VOH HIGH l level output ltt voltage out uts voltage; all outputs VCC = 2.7 V; VI = VIH or VIL; -IO = 100A VCC = 3.0 V; VI = VIH or VIL; -IO = 100A VCC = 4.5 V; VI = VIH or VIL; -IO = 100A VO OH HIGH level output voltage; g STANDARD outputs VCC = 3.0 V; VI = VIH or VIL; -IO = 6mA VCC = 4.5 V; VI = VIH or VIL; -IO = 12mA VCC = 1.2 V; VI = VIH or VIL; IO = 100A VCC = 2.0 V; VI = VIH or VIL; IO = 100A VOL LOW l ltt level output voltage out uts voltage; all outputs VCC = 2.7 V; VI = VIH or VIL; IO = 100A VCC = 3.0 V; VI = VIH or VIL; IO = 100A VCC = 4.5 V; VI = VIH or VIL; IO = 100A VO OL LOW level output voltage; g STANDARD outputs Input leakage current Quiescent supply current; MSI Additional quiescent supply current per input VCC = 3.0 V; VI = VIH or VIL; IO = 6mA VCC = 4.5 V; VI = VIH or VIL; IO = 12mA VCC = 5.5 V; VI = VCC or GND VCC = 5.5 V; VI = VCC or GND; IO = 0 VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V 1.8 2.5 2.8 4.3 2.40 3.60 1.2 2.0 2.7 3.0 4.5 2.82 4.20 0 0 0 0 0 0.25 0.35 0.2 0.2 0.2 0.2 0.40 0.55 1.0 20.0 500 0.2 0.2 0.2 0.2 0.50 V 0.65 1.0 160 850 A A A V 1.8 2.5 2.8 4.3 2.20 V 3.50 V 0.9 1.4 2.0 0.7II ICC ICC
NOTE: 1. All typical values are measured at Tamb = 25C.
1998 May 07
5
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165
AC CHARACTERISTICS
GND = 0V; tr = tf 2.5ns; CL = 50pF; RL = 1K SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 2.0 tPLH/tPHL Propagation delay CE, CP to Q7, Q7 Figures 1, 2 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 tPLH/tPHL Propagation delay PL to Q7, Q7 Figures 1, 2 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 tPLH/tPHL Propagation delay D7 to Q7, Q7 Figures 1, 2 2.7 3.0 to 3.6 4.5 to 5.5 2.0 tw Clock Pulse width HIGH or LOW 2.7 Figures 1 2 1, 3.0 to 3.6 4.5 to 5.5 2.0 tw Parallel load pulse width LOW 2.7 Figures 1 2 1, 3.0 to 3.6 4.5 to 5.5 1.2 2.0 trem Removal time PL to CP, CE Figures 1, 2 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 tsu Set-up time DS to CP, CE Figures 1, 2 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 tsu Set-up time CP CE to CP; CP to CE Figures 1, 2 2.7 3.0 to 3.6 4.5 to 5.5 20 15 - 24 18 17 12 - 22 16 13 9 - 22 16 13 9 20 15 34 25 MIN - - - - - - - - - - - - - - - 34 25 LIMITS -40 to +85 C TYP1 115 38 27 222 15 110 35 24 202 14 90 28 20 172 11 10 8 72 5 10 8 72 5 40 15 11 102 7 -8 -2 -1 -12 0 20 7 5 42 3 45 32 27 18 - - - - - - - - - - - - - - - - - - - - - - - 56 39 33 22 61 43 36 24 MAX -40 to +125 C MIN - - - - - - - - - - - - - - - 41 30 24 18 41 30 24 18 - 30 23 21 15 - 26 19 15 10 - 26 19 15 10 56 40 33 22 - - ns - - - - ns - - - - - - - - - - - - - - - - - ns ns ns ns 70 49 41 27 ns 76 54 45 30 ns MAX UNIT
1998 May 07
6
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165
AC CHARACTERISTICS (Continued)
GND = 0V; tr = tf 2.5ns; CL = 50pF; RL = 1K SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 2.0 tsu Set-up time Dn to PL Figures 1, 2 2.7 3.0 to 3.6 4.5 to 5.5 1.2 Hold time Ds to CP, CE Dn to PL 2.0 Figures 1, 2 2.7 3.0 to 3.6 4.5 to 5.5 1.2 th Hold time CE to CP, CP to CE t 2.0 Figures 1, 2 2.7 3.0 to 3.6 4.5 to 5.5 2.0 fmax Maximum clock pulse frequency Figures 1 2 1, 2.7 3.0 to 3.6 MIN - 22 16 13 9 - 22 16 13 9 - 5 5 5 5 14 19 24 36 -40 to +85 C TYP1 25 8 6 52 4 20 7 5 4 3 -30 -8 -6 -52 -4 40 60 652 75 MAX - - - - - - - - - - - - - - - - - - - -40 to +125 C MIN - 26 19 15 10 - 26 19 15 10 - 5 5 5 5 12 16 20 30 MAX - - - - - - - - - - - - - - - - - - - MHz ns ns ns UNIT
th
4.5 to 5.5 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25C 2. Typical values are measured at VCC = 3.3 V.
AC WAVEFORMS
VM = 1.5 V at VCC 2.7 V. VM = 0.5 x VCC at VCC < 2.7 V; VOL and VOH are the typical output voltage drop that occur with the output load.
1/fmax VI CP INPUT GND tW tPHL VOH Q7 or Q7 OUTPUT VOL The changing to output assumes internal Q6 opposite state from Q7. GND VM VOH tPHL tPLH VM VI PL INPUT GND tW trem VI CE, CP INPUT VM VM
SV00590
Q7 or Q7 OUTPUT VOL
VM
Figure 1. Clock (CP) to output (Q7 or Q7) propagation delays, the clock pulse width and the maximum clock frequency. Note to Figures 1 and 2 The changing to output assumes internal Q6 opposite state from Q7.
The changing to output assumes internal Q6 opposite state from Q7.
SV00591
Figure 2. Parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel load to clock (CP) and clock enable (CE) removal time.
1998 May 07
7
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165
AC WAVEFORMS
VM = 1.5 V at VCC 2.7 V. VM = 0.5 x VCC at VCC < 2.7 V; VOL and VOH are the typical output voltage drop that occur with the output load.
VI D7 INPUT GND tPLH VOH Q7 OUTPUT VOL tPHL VOH Q7 OUTPUT VOL VM Vl VO D.U.T. RT 50pF CL RL= 1k tPLH VM tPHL VM VI PL INPUT GND VM VI Dn INPUT GND tsu tH tsu tH VM
SV00593
Figure 5. Set-up and hold times from the data inputs (Dn) to the parallel load input (PL).
TEST CIRCUIT
Vcc
SV00592
PULSE GENERATOR
Figure 3. Data input (Dn) to output (Q7 or Q7) propagation delays when PL is LOW.
see note
Test Circuit for Outputs DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitiance RT = Termination resistance should be equal to ZOUT of pulse generators.
VI CP, CE INPUT GND VM
tsu (L) VI DS INPUT GND tsu th VI CP, CE INPUT GND VM tW th stable VM
tsu (H)
th
TEST tPLH/tPHL
VCC < 2.7V 2.7-3.6V 4.5 V
VI VCC 2.7V VCC
SV00902
Figure 6. Load circuitry for switching times.
CE may change only from HIGH-to-LOW while CP is LOW. The shaded areas indicate when the input is permitted to change for predictable output performance. SV00595
Figure 4. Set-up and hold times from the serial data input (DS) to the clock (CP) and the clock enable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock enable input (CE). Note to Figure 4 CE may change only from HIGH-to-LOW while CP is LOW. The shaded areas indicate when the input is permitted to change for predictable output performance.
1998 May 07
8
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
1998 May 07
9
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1998 May 07
10
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
1998 May 07
11
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
1998 May 07
12
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165
NOTES
1998 May 07
13
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74LV165
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04432
Philips Semiconductors
1998 May 07 14

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